Multilayer structures have been developed and devised which include an electrical substrate and laminated layers of an optical waveguide.
A device or optical chip including a light-emitter (VCSEL, etc.) or photoreceptor (PD, etc.), which operates in optical contact with an optical waveguide, requires electrical contact with an electrical substrate to operate electrically.
A via for electrical contact passing through the layers of the optical waveguide is known to be used for this purpose.
FIG. 1 and FIG. 2 are diagrams used to explain the formation of a via for electrical contact in the prior art.
Note that FIG. 1 and FIG. 2 are consecutive.
In order to establish an electrical substrate combining an insulating layer and a conductive layer, an insulating layer and copper wiring are formed as shown in (1).
In the prior art, a via hole is formed by removing a portion of the insulating layer as shown in (2).
In the prior art, pre-treatment is performed and a seed layer is formed as shown in (3).
In the prior art, a resist pattern is formed as shown in (4).
In the prior art, copper wire is formed which fills the formed via hole as shown in (5).
Wiring formed to reach a different layer in this way is called a “via”, more specifically, a “filled via”.
In the prior art, the resist pattern is stripped as shown in (6).
In the prior art, the seed layer is etched as shown in (7).
The rest of the process involves the formation of a multilayer structure including the electrical substrate and the laminated layers of the optical waveguide.
In the prior art, the layers of the optical waveguide are formed as shown in (8).
A core is surrounded by an underclad and an overclad so that light propagates through the core.
The core and the clads have different refractive indices.
In the prior art, some of the layers of the optical waveguide are removed to form a via hole.
In the prior art, pre-treatment is performed and a seed layer is formed as shown in (10).
The seed layer is formed so that electricity is supplied to the portion requiring plating when copper plating is performed later.
The seed layer is generally formed using electroless plating. At this time, the electroless plating solution penetrates into the gaps between the copper wiring and underclad.
Because the materials in the optical waveguide have poor chemical resistance, the processing time using chemical products has been intentionally shortened.
Such a process should be eliminated if possible.
In the prior art, a resist pattern is formed as shown in (11).
In the prior art, copper plating is performed on the via hole, and copper wiring filling the via hole is formed as shown in (12).
Here, a filled via is formed, but this causes the distance between the chip and mirror to be lengthy after bonding. This problem is explained in greater detail below.
In the prior art, gold plating is formed on the upper surface of the filled via as shown in (13).
This is used as an electrode pad.
Gold has superior characteristics such as corrosion resistance and good electrical contact, but the mechanical strength of gold bonding is insufficient. This problem is explained in greater detail below.
In the prior art, the resist pattern is stripped as shown in (14).
In the prior art, the seed layer is etched as shown in (15).
Finally, in the prior art, a portion of the layers of the optical waveguide are removed to install a mirror as shown in (16).
Typically, optical contact is established with a light-emitter (VCSEL, etc.) emitting light on a plane or a photoreceptor (PD, etc.) receiving light on a plane by converting the direction of light to 45 degrees.
FIG. 3 is a diagram showing the configuration of the electrical contact between the device or optical chip and the electrical substrate in the prior art.
The device or chip has a stud (pillar), and the stud (pillar) is bonded to the gold plating on top of the electrical substrate serving as an electrode pad.
A bond with the gold is formed by applying pressure and squashing the gold. However, because the cross-sectional area of contact is limited, the mechanical strength is insufficient.
The cross-sectional area of contact also affects the electrical resistance of the current flowing through.
In addition, a long portion of the stud (pillar) remains in place, and this lengthens the distance between the chip and the mirror after bonding.
Because a long distance between the chip and mirror is linked to insertion loss, this distance should be as short as possible.
When there is a direction conversion error (for example, 45°±α°), a longer distance makes it more difficult to position the light-emitter or photoreceptor.
Patent Literature 1, Patent Literature 2 and Patent Literature 3 all address the technical problem of reducing insertion loss by bringing the chip and mirror closer together by forming a via in a region of the optical waveguide.
However, none of them mentions one of the characteristics of the present invention, which is to form a via by removing a portion of the optical waveguide.
Patent Literature 4, Patent Literature 5 and Patent Literature 6 describe the mounting of an optical chip, but none of them disclose or suggest the important point mentioned above.
Patent Literature 1-6 is listed below.